Open-source ASIC design

This course introduces the principles and methodologies of open-source Application-Specific Integrated Circuit (ASIC) design, covering the complete flow from high-level synthesis (HLS) to layout generation. The course provides students with practical knowledge of state-of-the-art open-source EDA tools and frameworks, enabling them to perform RTL synthesis, place and route, static timing analysis, and design rule checking using publicly available technologies and PDKs. Through a step-by-step workflow, students will learn how to transform a high-level behavioral description into a manufacturable GDSII layout, gaining hands-on experience with tools such as Yosys, OpenROAD, and OpenLane.

Target audience

Advanced MSc students, PhD students, researchers, and professionals seeking practical experience with open-source ASIC flows 

Learning outcomes 

• The student understands the complete digital design flow from HLS to GDSII using open-source tools.
• The student can synthesize and analyze RTL code using Yosys and perform place-and-route with OpenROAD/OpenLane.
• The student is able to identify timing and physical design issues, applying appropriate optimization strategies.
• The student gains practical experience with open PDKs and understands how open ASIC design enables education, research, and prototyping.

Syllabus

Module 1: Flow and ecosystem

End-to-end ASIC flow, open-source EDA landscape, and the file formats you will work with. You learn how to read run outputs and reports to navigate the flow with an engineering mindset.

Module 2: HLS fundamentals

How HLS maps code to hardware, and how to write HLS-friendly code that synthesizes predictably. You cover verification of HLS-generated RTL and the main knobs that trade performance, area, and closure risk.

Module 3: RTL synthesis

How RTL becomes a mapped gate-level netlist and why technology mapping choices matter. You learn to read synthesis reports and debug RTL issues that would otherwise poison timing and PnR.

Module 4: Timing and constraints

Core STA concepts and how to write minimal but meaningful SDC constraints. You practice fast triage of timing failures and apply pre-PnR fixes that improve feasibility before physical design.

Module 5: Physical design

How early physical decisions set the routability and timing “budget” for the whole chip. You learn what to watch after placement and CTS, and how to debug physical issues without random tuning.

Module 6: Routing and optimization

Global vs detailed routing, typical routing failure modes, and how parasitics change timing after route. You cover hold-fix concepts and adopt an iteration strategy that keeps progress measurable and stable.

Module 7: Physical verification

DRC and LVS goals, common violation/mismatch classes, and a practical verification workflow with decision gates. You learn how to write a credible signoff summary backed by evidence and explicit assumptions.

Module 8: Tapeout readiness and release

What an open PDK provides, how PDK views must stay consistent, and what MPW/tape-out workflows expect. You define what is a final release and how to package a reproducible run with a manifest and archived reports.

Instructor

Christian Pilato, Politecnico di Milano